The present invention relates to a semiconductor device packaged by implementing a plurality of semiconductor devices in a mounting board, and to, for example, a technique effective if applied to a semiconductor device configured as a multichip module or SIP (System in Package) in which a synchronous DRAM (SDRAM) chip having a double data rate (DDR) based on the JEDEC standard (JESD79) and a microcomputer chip are mounted.
External data terminals of plural bits in an SDRAM are configured in such a manner that their data input/output timings are synchronized with a clock signal. A microcomputer fetches therein data outputted from the SDRAM in sync with the clock signal (data strobe signal: DQS) outputted from the SDRAM. As data input/output rates of the SDRAM, there are known a single data rate, and a double data rate equivalent to twice the single data rate. The single data rate inputs and outputs data in cycle units of the data strobe signal, whereas the double data rate inputs and outputs data in sync with the falling and rising edges of the data strobe signal. Thus, a timing margin is reduced in the double data rate as compared with the single data rate. Achieving an improvement in signal integrity (SI) with respect to in-module wirings connected to data input/output data terminals (DQ) doubled in transfer rate and data strobe terminals (DQS) for the input/output of the data strobe signal therefore needs to prevent malfunctions in particular.
Although attention is not directed toward the improvement in the signal integrity, a semiconductor device in which a microprocessor and a DDR-SDRAM are mounted onto one printed circuit board or mounting board has been described in a patent document 1 (Japanese Unexamined Patent Publication No. 2003-204030).